A conventional speed variation control method is explained below. Conventionally, speed of, for example, a motor is varied by varying a command speed at every fixed interval. This method is called as a fixed time interval method in the explanation that follows.
FIG. 12 is a block diagram of a positioning unit that employs the fixed time interval method. A reference numeral 101 represents a speed-adjustment control block, 112 represents a central processing unit (CPU) or a computing unit (hereinafter, “computing unit”), 113 represents a variable frequency pulse generating circuit, and 114 represents a position control circuit.
The speed adjustment control block 101 includes the computing unit 112. A setting value, a reference clock, an interrupt signal, number of output pulses are input into the computing unit 112 from outside. The computing unit 112 generates and outputs a speed command value and a control signal and a setting value related to position.
The variable frequency pulse generating circuit 113 calculates a pulse string fout of variable frequency based on the speed command value-output from the computing unit 112 in the speed adjustment control block 101, and outputs the pulse string fout.
The position control circuit 114 receives the pulse string, counts this pulse string and outputs the number of output pulses to the speed adjustment control block 101. In addition to that, the position control circuit 114 compares the control signal and the setting value related to position that are received from the speed adjustment control block 101 with number of output pulses and generates a stop signal when a prescribed positioning is completed.
When the stop signal is validated, the variable frequency pulse generating circuit 113 stops the output of the pulse string.
FIG. 13 is a graph of speed variation in the fixed time interval method. In FIG. 13, a horizontal axis indicates time, a vertical axis indicates speed and an area indicates amount of shift (number of output pulses). The speed is varied (accelerated or decelerated) by varying the number of pulses output for each time interval of speed variation (control cycle: Δtc=fixed value).
During acceleration, number of divisions (CTa—where ‘a’ stands for acceleration) of acceleration time is calculated and taken as number of divisions (Cva) of |command speed (VS)−initial speed (V0)|. The speed is controlled by determining the number of pulses (ΔY(m)a) that are output in time Δtc.
The number of divisions during acceleration CTa is a quotient of ta/Δtc. Speed increment ΔV(m)a with respect to initial speed (V0) is ΔY(m)a/Δtc. Speed increment ΔV(m−1)a with respect to V0, which is just before ΔV(m)a is ΔV(m−1)a/Δtc. Amount of variation in speed [ΔV(m)a−ΔV(m−1)a] becomes ΔY(m)a/Δtc−ΔY(m−1)a/Δtc≈|command speed (VS)−initial speed (V0)|/Cva. Here, m=(1, 2, . . . , (Cva−1), Cva).
During deceleration, number of divisions (CTd—where ‘d’ stands for deceleration) of deceleration time is calculated and taken as number of divisions (Cvd) of |command speed (VS)−initial speed (V0)|. The speed is controlled by determining the number of pulses ((ΔY(n)d) that are ouput in time Δtc.
The number of divisions during deceleration CTd is a quotient of td/Δtc. Speed increment ΔV(n)d with respect to initial speed (V0) is ΔY(n)d/Δtc. Speed increment ΔV(n−1)d with respect to V0, which is just prior to ΔV(n)d is ΔV(n−1)d/Δtc. Amount of variation in speed [ΔV(n)d−ΔV(n−1)d] becomes ΔY(n)d/Δtc−ΔY(n−1)d/Δtc≈|command speed (VS)−initial speed (V0)|/Cvd. Here, n=(Cvd, (Cvd−1), . . . ,2, 1).
The operation of the fixed time interval method is explained below with reference to FIG. 12 and FIG. 13.
The variable frequency pulse generating circuit 113 is not activated at this stage. The computing unit 112 calculates the amount of shift at the start of deceleration and calculates the number of pulses to be output ΔY(m)a (=ΔY(1)a)+V0 that is to be output in first Δtc.
When the calculation is finished, the ΔY(m)a+V0, which is calculated earlier, is output to the variable frequency pulse generating circuit thereby activating the variable frequency pulse generating circuit. Thereafter, the computing unit 112 goes on calculating the following ΔY(m)a+V0 for each Δtc and outputting the ΔY(m)a+V0 to the variable frequency generating circuit 113 (goes on accelerating).
The calculation and output of the following ΔY(m)a+V0 is carried out within time Δtc. In a short time, process in the command speed (VS) is carried out. While decelerating, when counter value that is counting remaining amount of shift in real time reaches the amount of shift at the start of deceleration, it goes on decelerating with the speed of ΔY(n)d+V0. When the remaining amount of shift becomes ‘0’, the variable frequency pulse generating circuit 113 is stopped. Here, m=(1, 2, . . . , (Cva−1), Cva), n=(Cvd, (Cvd−1), . . . ,2, 1).
A control method by varying speed in which number of divisions of speed adjustment time is fixed, speed adjustment time (acceleration or deceleration time) is divided by the number of divisions (fixed value) and the speed is varied at each time interval that is obtained from the result of the division, is available as another conventional method of speed variation control. This method is called as fixed number of divisions method in the following explanation.
FIG. 14 is a block diagram of a positioning unit that employs the fixed number of divisions method. A reference 102 is a speed adjustment control block, 120 is a timing generating circuit, 121 is a memory table, 122 is a CPU or a computing unit (hereinafter, “computing unit”), 123 is a variable frequency pulse generating circuit, and 124 is position control circuit.
The speed adjustment control block 102 includes the timing generating circuit 120, the memory table 121, and the computing unit 123. A setting value, reference clock are input to the computing unit 122 from outside. The computing unit 122 calculates command speed Vp(j). The speed Vp(j) that is made to vary for each Δta(j) is expressed in terms of a reference clock frequency of the pulse generating circuit Vpp(j). The computing unit 122 also calculates speed variation timing Δta(j) during acceleration in terms of (1/base block frequency for interrupt signal) Δtap(j) and remaining distance ΔYd(g) during deceleration. The computing unit 122 writes the values of Vp(j), Δta(j), and ΔYd(g) in the memory table 121.
Moreover, the computing unit 122 divides the speed adjustment time by the number of divisions (fixed value) and provides the resultant value of the division to the timing generating circuit 120. The timing generating circuit 120 generates an interrupt signal for each time interval provided and outputs to the computing unit 122. The computing unit 122 varies the speed command using the data in the memory table 121 and outputs to the variable frequency pulse generating circuit 123. In addition to this, the computing unit 122 outputs the control signal and the setting value related to position, current speed, and number of output pulses.
The speed command generated in the speed adjustment control block 102 is provided to the variable frequency pulse generating circuit 123 thereby obtaining pulse string of variable frequency.
The position control circuit 124 receives the pulse string, counts it and returns the number of output pulses to the speed adjustment control block 102. In addition to this, the position control circuit 124 compares the control signal and the setting value related to position that are received from the speed adjustment control block 102 with number of output pulses, and generates deceleration start signal and stop signal. Thereafter, the position control circuit 124 outputs these signals to the speed adjustment control block 102 and to the variable frequency pulse generating circuit 123. The deceleration starts when deceleration start signal is validated and the output pulse stops when the stop signal is validated.
Here, Vpp(j) is [([(number of divisions (Cvc) of |command speed(VS)−initial speed|/|command speed (VS)−initial speed)×j+initial speed]×(1/reference clock frequency of pulse generating circuit))—where numbers of five and above are rounded and anything under five is dropped]. Command speed Vp(g) that is made to vary for each ΔYd(g) is expressed in terms of reference clock frequency of the pulse generating circuit and becomes [([(number of divisions (Cvc) of |command speed(VS)−initial speed|/|command speed (VS)−initial speed|)×g+initial speed]×(1/reference clock frequency of pulse generating circuit))—where numbers of five and above are rounded and anything under five is dropped].
Δtap(j) is equal to [([acceleration time/number of divisions (CTc) of acceleration time]×j×reference clock frequency for interrupt signal)—where numbers of five and above are rounded and anything under five is dropped].
ΔYd(g) is a remaining number of pulses of the output pulse which becomes [(Vpp(g)×reference clock frequency of the pulse generating circuit+initial speed)×(deceleration time/number of divisions (CTc) of the deceleration time)×g]/2. Here, j=(1, 2, . . . , (Cvc−1), (Cvc)), g=(Cvc, (Cvc−1), . . . , 2,1).
FIG. 15 is a graph of speed variation in the fixed number of divisions method. In FIG. 15, a horizontal axis indicates time, a vertical axis indicates speed and an area indicates amount of shift (number of output pulses). The speed is varied by determining the amount of variation in speed, variation time, and the amount of shift remained when the number of divisions (Cvc) of |command speed (VS)−initial speed| and the number of divisions (CTc) of the speed adjustment time (acceleration or deceleration time) are fixed values.
During acceleration, [Δta(j)]≈(ta/CTc×j) indicates speed variation timing from the start of acceleration and after elapsing of time [Δta(j)] the speed variation is controlled by varying speed increment [ΔV(j)] with respect to V0.
During deceleration, a value obtained by subtracting a current value of number of output pulses from amount of command shift is counted (amount of shift that is remained, is indicated in real time). When this calculated value reaches the amount of shift remained, the speed increment [ΔV(g)] with respect to V0 is made to vary, thereby controlling the speed variation.
The amount of variation in speed [ΔV(j))−ΔV(j−1)] becomes [ΔV(g)−ΔV(g−1)]≈(|command speed (VS)−initial speed|/Cvc). Here, j=(1, 2, . . . , (Cvc−1), Cvc) and g=(Cvc, (Cvc−1), . . . , 2, 1).
The operation in the fixed number of divisions method is explained below while referring to FIG. 15 and FIG. 16.
The variable frequency pulse generating circuit 123 is not activated at this stage. The computing unit 122 calculates the Δtap(j), Vpp(j)=Vpp(g) required at the time of acceleration, ΔYd(g) required at the time of deceleration and writes values of Δtap(j), Vpp(j)=Vpp(g) and ΔYd(g) in the memory table 121.
The variation frequency pulse generating circuit is activated. Therefore, acceleration is carried out with the speed Vp=[ΔV(j)+V0] for each ΔYd(g). Thereafter, when the counter value, which is counting the amount of shift remained in real time, reaches ΔYd(g), deceleration is carried out with the speed of Vp=[ΔV(g)+V0] and when the amount of shift remained becomes ‘0’, the variable frequency pulse generating circuit 123 stops. Here, j=(1, 2, . . . , (Cvc−1), Cvc) and g=(Cvc, (Cvc−1), . . . , 2, 1).
Japanese Patent Application laid open Publication No. 1998-42597 discloses a stationary recording disc in an information recording apparatus. This publication teaches use of an acceleration region that is increased in form of steps, for frequency step range Δf a value obtained by dividing [target frequency (rated number of revolutions region) f3−starting speed f2] by 8. This is a method in which time range Δt corresponding to the value of Δf obtained is made to be Δt=t2/8.
In the fixed time interval method, since the time interval is fixed, as the speed adjustment time becomes short, the number of divisions of time and the number of divisions of speed become smaller and the amount of variation in speed becomes large. Due to the large amount of variation in speed the stepping motor becomes apt to lose synchronism (misstepping), which is a problem in this conventional method.
Generally, in positioning control carried out by the fixed time interval method, it is necessary to increase the number of divisions to avoid the loss of synchronism. However, since calculation is carried out one after another for each control cycle Δtc, there is always load on calculating machine (microcomputer, computing unit etc.) and it is not possible to deal with increased number of control axes. In such case, it is necessary to make the control period Δtc long or to improve performance of the calculating machine or to increase the number of calculating machines. However, improving the performance of the calculating machine increases the cost, increasing of number of clocks makes it weaker to noise, and increasing the number of calculating machines results in increase in mounting area, thereby making the size bigger. Consequently, increasing of control axes proved to be disadvantageous.
Furthermore, the speed during the speed adjustment does not change in multiples of minimum speed and correct monitoring of speed becomes impossible.
Moreover, in positioning control carried out by the fixed time interval method, it is necessary to increase the number of divisions considering the performance of the calculating machine to avoid the loss of synchronism. Therefore, the speed adjustment time has to be set longer which results in a longer tact time (positioning time).
FIG. 16 is a graphical representation of problems in the fixed time interval method. A graph 2 is obtained with the conventional fixed time interval method, a graph 1 is obtained according to the present invention, and a graph 3 is obtained with another conventional fixed number of divisions method. As is clear from this figure, since the time interval is fixed, the speed variation during acceleration in graph 2 is in the form of steep steps.
On the other hand, in the fixed number of divisions method, since the number of divisions is fixed, as the value of |command speed (VS)−initial speed| becomes bigger, the amount of variation in speed also increases thereby making the stepping motor apt to lose synchronism.
Generally, in positioning control carried out by the fixed number of divisions method, it is necessary to set the speed adjustment time longer. However, when the speed adjustment time is set to be longer, the tact time (positioning time) becomes longer.
Moreover, it is necessary to increase the number of divisions so as to decrease the amount of variation in speed, and increase in number of divisions results in increase in values of Δta(j), ΔV(j), and ΔYd(g). Due to this, calculating time and time for writing in memory increase and time before start up becomes longer. This results is the tact time becoming longer and also it is necessary to increase memory that stores Δta(j), ΔV(j), and ΔYd(g), thereby increasing cost and required space.
Furthermore, the speed during the speed adjustment does not change in multiples of minimum speed and correct monitoring of speed becomes impossible.
FIG. 17 is a graphical representation of problems in the fixed number of divisions method. Graph 6 is obtained with the conventional fixed number of divisions method, graph 4 is obtained according to the present invention, and graph 5 is obtained with another conventional fixed time interval method. As is clear from this figure, since the number of divisions is fixed, the speed variation during acceleration in graph 6 is in the form of steep steps.
About the speed variation control method from the starting speed f2 up to the target frequency (rated number of revolutions region f3) is not mentioned in the Japanese Patent Application Laid Open Publication No. 1998-42597. Therefore, it is not known whether it is possible to shorter the acceleration time according to the technology disclosed in this publication. Also, time required for preparatory calculation and load of calculation process is not known.
It is an object of the present invention to solve at least the problems in the conventional technology.